A reconfigurable integrated circuit, represented by FPGA (Field Programmable Gate Array) that is able to alter its circuit configuration arbitrarily, is a device which stores circuit configuration information in a storage cell built in the device to allow for freely and flexibly altering its connection status of routing wires, logic functions in logic blocks, or interconnection status between the routing wire and the logic block. A user can configure a logic circuit with desirable scale and functions by externally writing the circuit configuration information in the storage cell within the device.
In order to implement a flexible reconfiguration function in the reconfigurable integrated circuit, a plurality of programmable routing switches are implemented in a plurality of basic circuit blocks as well as a plurality of routing switch blocks to control the connection status between the basic circuit blocks.
The programmable routing switch is configured by a field effect transistor with a switch function (switch FET) and a storage cell for storing a conducted or non-conducted status of the switch FET.
By connecting the wires between the routing wires or between the routing wire and the logic block via the programmable routing switch, a connected or disconnected status between the routing wires or between the routing wire and the logic block can be determined by a stored status of the storage cell built in the programmable routing switch.
The programmable routing switch has a plurality of input terminals and a single output terminal, and also has a plurality of switch FETs that configure a multiplexer circuit capable of selectively outputting signal voltage from the plurality of input terminals, and a plurality of storage cells for storing the conducted or non-conducted status of the switch FETs that configure the multiplexer circuit. These storage cells employ SRAM (Static Random Access Memory).
Patent Documents 1-6 have proposed the programmable routing switch using the non-volatile storage cells as information storage cells for the purpose of anti-tapping of configuration information of the FPGA or reduction in the power consumption of the programmable routing switch, particularly the storage cells.
For example, the programmable routing switches provided with the non-volatile storage cells, as described in Patent Document 1 or 2, employs a configuration in which the switch FET shares a floating gate with a device having functions of tunneling electrons and of verifying an accumulated charge amount of the floating gate, and two FETs configure a single basic device.
In addition, the programmable routing switch provided with the non-volatile storage cells, as described in Patent Document 3, 4, 5, or 6 employs a configuration in which the switch FET shares a floating gate with a device having a function of tunneling electrons and a device having a function of verifying an accumulated charge amount of the floating gate, and three FETs configure a single basic device.
Patent Document 1: U.S. Pat. No. 5,838,040
Patent Document 2: U.S. Pat. No. 5,633,518
Patent Document 3: U.S. Pat. No. 5,773,862,
Patent Document 4: U.S. Pat. No. 5,894,148
Patent Document 5: U.S. Pat. No. 5,764,096
Patent Document 6: U.S. Pat. No. 6,252,273